1. Field of the Invention
The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit for controlling the discharge current which flows when the ground potential is output.
2. Description of the Prior Art
As a final output means of a semiconductor memory circuit, for example, an output buffer circuit shown in FIG. 1 is conventionally used. In this circuit, when a control signal C is at an inactive level (high level), a P-channel type transistor 1 and an N-channel type transistor 2 constituting an output transistor are turned OFF. Meanwhile, when the control signal C is ON an active level (low level), either of the P-channel type transistor 1 or the N-channel type transistor 2 is turned ON to generate an output signal B on the high or low level in accordance with a level of an input signal A in this circuit. To a gate of the N-channel type transistor 2 is connected an N-channel type zero-threshold transistor 11. The reason why this transistor 11 is provided is described as follows. If the transistor 11 is not provided, the N-channel type transistor 2 rapidly responds to a change in the input signal A to perform the ON/OFF operation. In particular, when the N-channel type transistor 2 is turned from the OFF state to the ON state, there occurs such a problem that a large amount of the current instantaneously flows to a ground power supply GND, increasing the ground potential (noise generation). As a countermeasure, to the gate of the N-channel type transistor 2 is connected the transistor 11 which functions as a resistance element which receives at a gate thereof a predetermined voltage S supplied from a constant voltage generation circuit 50 and has a predetermined resistance value. The speed of change in the gate potential of the transistor 2 is decreased because of the existence of the transistor 11. In other words, the speed of the ON/OFF operation of the transistor 11 is decreased, and consequently, a large amount of the current does not flow to the ground power supply instantaneously, preventing the ground potential from being increased.
The buffer circuit shown in FIG. 1, however, has such a problem that the speed of the output operation is decreased since an input signal is always supplied to the gate of the transistor 2 through the transistor 11 functioning as the resistance element.
There is a prior art circuit (Japanese Patent Application Laid-Open No. Hei-4-37216 (1992), for example) which can selectively changeover the speed of the change in the gate potential of the output transistor, as shown in FIG. 2. The ON/OFF operation of an N-channel type transistor 54 is controlled by changing over the potential of a control terminal T, and the control is made upon whether the input signal is supplied through a P-channel type transistor 53 functioning as the resistance element.
With this prior art circuit, it is not possible to solve both of the problems, i.e., the increase of the ground potential and the decrease of in speed of the output operation, simultaneously. That is, when the potential of the control terminal T is at the low level, the transistor 54 is turned OFF. At this time, for example, when an input signal A is turned from the high level to the low level, the level of a gate potential 3 of a transistor 1 immediately becomes the high level, but the gate potential is slowly increased due to the transistor 53 functioning as the resistance element. Thus, the increase in the ground potential can be prevented similarly to the prior art shown in FIG. 1, but the speed of the output operation is decreased.
When the potential of the control terminal T is at the high level, the transistor 54 is turned ON. Since the resistance of the transistor 54 which is in the ON state is small, the gate potential 3 of the transistor 1 and a gate potential 4 of the transistor 2 rapidly vary in response to the change in the input signal A. Therefore, the speed of the output operation is increased, but a large amount of the current flows to the ground power supply GND, thereby rapidly increasing the ground potential.
As apparent from the above description, the conventional output buffer circuit can not prevent the rapid increase of the ground potential without decreasing the output operation speed.